four-channel cx29704, two-channel cx29702, one-channel cx29701 155mbps atm/pos phy with clock and data recovery the cx2970x is an integrated circuit that implements four-channel atm/packet over sonet/sdh (pos) processing functions at 155.52 mbps. the device contains both the pmd and tc sublayers and features a utopia level 2 interface to the atm layer or, optionally, a pos phy level 2 interface to the link layer. this device also includes dedicated serial ports for the insertion and extraction of the dcc overhead bytes. sonet/sdh processing in the transmit path, this device generates all section, line and path overhead bytes, in addition to implementing framing, scrambling and alarm indication functions. on the receive path, all framing, descrambling, alarm detection and pointer interpretations are performed. a serial interface inserts and extracts the section or line dcc bytes. atm cell processing for atm cell processing, the cx2970x performs all cell encapsulation, hec calculation, cell delineation, payload scrambling/descrambling and idle cell insertion/filtering. data is exchanged with a higher-layer device using a utopia level 2 interface. pos processing in pos mode, the cx2970x performs all hdlc framing, scrambling/descrambling, interframe fills, fifo management and stuffing/destuffing operations. data is exchanged with higher-layer devices using a pos phy level 2 interface. line interface the cx2970x includes on-chip clock and data recovery (cdr) for 155.52 mbps line rates. this cdr block also implements the serialize/deserialize functions. on the receive path, after recovery of the data and its associated clock, data is sent to the sonet/sdh framer via a parallel bus. higher-layer interface the cx2970x supports several interfaces to higher- layer devices. the component supports a utopia le vel 2 interface for atm cells and a pos phy interface for ppp packets in pos mode. up to eight cx2970x devices can be connected to a single higher-level device (multiport atm-layer or pos-layer device), in various operation modes. > integrated clock and data recovery (cdr) > clock recovery conforms to gr-253-core jitter requirements > low-power, 3.3 v cmos technology > synthesizes a 155 mhz tx clock from a 19 mhz input > utopia level 2 and pos level 2 system interfaces > > key features optiphy ? f155 quad oc-3/stm-1 atm/pos phy cx29704/2/1
www.mindspeed.com/salesoffices general information: (949) 579-3000 headquarters C newport beach 4000 macarthur blvd., east tower newport beach, ca 92660-3007 29704-brf-001-b m01-0361 ? 2003 mindspeed technologies ? . all rights reserved. mindspeed and the mindspeed logo are trademarks of mindspeed technologies. all other trademarks are the property of their respective owners. although mindspeed technologies strives for accuracy in all its publications, this material may contain errors or omissions and is subject to change without notice. this material is provided as is and without any express or implied warranties, including merchantability, fitness for a particular purpose and non- infringement. mindspeed technologies shall not be liable for any special, indirect, inci- dental or consequential damages as a result of its use. ? four fully configurable independent channels, supporting atm or pos ? fully integrated clock and data recovery module supporting a 155.52 mbps data stream ? sts-3c/stm-1 data-stream processing with mapping functions of atm cells or ppp packets into sonet/sdh payloads ? full processing of sonet/sdh section, line and path overhead bytes with dcc overhead interface ? access to all sonet/sdh overhead bytes via a microprocessor port ? utopia level 2 and pos phy level 2 interfaces to higher-layer devices ? optional sonet/sdh frame scrambling/descrambling operation (1+x6+x7) ? standard ieee 1149.1 jtag port ? complies with sonet/sdh standards (bellcore gr-253, itu-g.707 and ansi t1.105) ? complies with ppp protocol over sonet/sdh (rfc 1619/1662 of the ietf) ? 272-pin pbga package ? 3.3 v operation, with 5 v input tolerance applications ? switches ? routers ? dslams ? cellular base station infrastructure product features txd3+/- rxd3+/- sd3 txd0+ txd0- rxd0+ rxd0- sd0 refclk txd1+/- rxd1+/- sd1 port 3 port 2 port 1 port 0 txdata [15.0] txadd [4.0] txsoc/p [3.0] *txenb [3.0] txclav/ptpax4 tx_stpa txprty txclk t_err tx_eop tx_mod rxdata [15.0] rxadd [4.0] rxsoc/p [3.0] *rxenb [3.0] rxclav/prpax4 rx_rval rxprty rxclk rx_err rx_eop rx_mod parallel to serial tx sonet/sdh framer rx sonet/sdh framer tx overhead processor rx overhead processor serial to parallel data and clock recovery clock synthesis lpf 1 lpf 2 tx atm cell processor tx pos processor rx pos processor rx atm cell processor fifo fifo fifo fifo utopia level 2 / pos phy interface sec./line dcc i/f microprocessor interface jtag interface assi tsdcc 1-4 tsdck 1-4 tldcc 1-4 tldck 1-4 rsdcc 1-4 rsdck 1-4 rldcc 1-4 rldcc 1-4 d [7:0] a [5.0] *cs w/*r *dstb *intr asclk *asstb asdo tdo tdi tck tms *trst cx2970x block diagram
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